The Libre-SOC Project [EuroPython 2021 - Talk - 2021-07-30 - Brian] [Online] By Luke Leighton The Libre-SOC Project aims to bring to market a mass-volume System-on-a-Chip suitable for use in smartphones netbooks tablets and chromebooks, which is end-user programmable right to the bedrock. No spying backdoors, no treacherous DRM. Python and standard Libre Project Management is used throughout: * nmigen, a python-based HDL, is a fundamental and critical strategic choice in creating the hardware. * An IEEE754 FP hardware library has been developed using nmigen/python, as are hundreds of thousands of unit tests * An OpenPOWER ISA simulator is written in python, and is actually a PLY compiler based on the GardenSnake example * Several thousand unit tests for the HDL and simulator are written in python * coriolis2, the VLSI ASIC layout toolchain, is a mixed c++ python application * cocotb, a hardware co-simulation system, is used to verify the HDL is correct, down to the gate level * a JTAG "remote" system has been written in python which allows the simulated processor to be connected to with openocd. * Even the Standard Cell Library being used, called FlexLib, by Chips4Makers, is in python. To say that python is critical to the project would be a massive understatement. This talk will give a brief overview of the above areas and give a glimpse into why python was chosen for each. License: This video is licensed under the CC BY-NC-SA 4.0 license: https://creativecommons.org/licenses/by-nc-sa/4.0/ Please see our speaker release agreement for details: https://ep2021.europython.eu/events/speaker-release-agreement/